--
-- VHDL Architecture Fietssimulator_lib.state_machine.v
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp6241)
--          at - 17:01:45 14-04-2009
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY s_state_machine IS
  PORT( 
  X     : IN     STD_LOGIC;
  hex   : IN     STD_LOGIC;
  strb  : IN     STD_LOGIC;
  eos   : OUT    STD_LOGIC;
  test  : OUT    STD_LOGIC;
  clk   : IN     STD_LOGIC;
  rst   : IN     STD_LOGIC
  );
END ENTITY s_state_machine;

--
ARCHITECTURE v OF s_state_machine IS

TYPE statetype IS (PU, X0, H3, H2, H1, H0 );
SIGNAL state : statetype;

BEGIN
  
  
  
  
  PROCESS(rst, clk)
    BEGIN
      IF rst = '1' THEN
        
        test <= '0';
        eos   <= '0';
        state <= PU;
      ELSIF RISING_EDGE(clk) THEN
        
        CASE state IS
          
        WHEN PU =>
          
          eos <= '0';
          IF strb = '1' AND X = '1'  THEN   
            state <= X0;
          END IF;
          
          
        WHEN X0 =>
          test <= '1';
          IF strb = '1' THEN
            IF  hex = '1'  THEN   
              state <= H3;
            ELSE 
              state <= PU;
            END IF; 
          END IF;
          
        WHEN H3 =>   
          IF strb = '1' THEN
            IF  hex = '1'  THEN   
              state <= H2;
            ELSE 
              state <= PU;
            END IF; 
          END IF;
          
          
        WHEN H2 =>
          IF strb = '1' THEN
            IF  hex = '1'  THEN   
              state <= H1;
            ELSE 
              state <= PU;
            END IF; 
          END IF;
          
        WHEN H1 =>
          IF strb = '1' THEN
            IF  hex = '1'  THEN 
              state <= H0;
            ELSE 
              state <= PU;
            END IF; 
          END IF;
          
          
        WHEN H0 =>
          eos   <= '1';
          state <= PU;   
          
          
        END CASE; 
        
      END IF;
    END PROCESS;
    
    
    
  END ARCHITECTURE v;
  
  
  
  
  
  
  
  